In one Pipeline Readout Order of the SVX3 chip a pedestal shift is observed every 45th pipeline bucket of a dead-timelss map (a.k.a. pipeline scan). The shift is induced in the reference capacitor when a cell that has been flagged for readout by a Level 1 Accept is skipped over while the reference capacitor is in the pipeline read amplifier feedback loop. The mechanism that leads to the charge injection is not understood.
Postscript plot of a typical dead-timeless map showing average pedestal vs. bucket number for an SVX-II z hybrid.
A postscript scatter plot of the size of the pedestal shift in ADC counts vs. the number of chips in a hybrid. Red is SVX-II phi, black is SVX-II z, and blue is ISL.
A postscript 2-D lego plot of the size of the pedestal shift in ADC counts vs. the number of affected buckets within a 200-bucket dead-timeless map. Red is SVX-II phi, black is SVX-II z, and blue is ISL.
A list of what hybrids were looked at to make the above plots.