Pedestal slope vs. pipeline cell number (a.k.a. 10% buffer noise)

The pedestal of an arbitrary channel in the SVX3 chip is supposed to be the same for every choice of pipeline cell. However, the pipeline circuitry covers a large area of silicon, and variation of process parameters (such a oxide thickness) as a function of position on the wafer can lead to dependence of the pedestal on pipeline cell ID as well as channel number. Since one normally bins data in terms of channel number pedestal vs. channel variations are obvious to notice, but a pedestal variation vs. cell ID will typically show up as an effective increase in RMS noise. In reality there is no true noise increase and if one averages the data in bins of cell ID instead of channel number the "hidden" pedestal structure can be revealed.

This Postscript plot shows the distribution of pedestal slope vs. cell ID for a number of SVX3 chips on both SVX-II and ISL hybrids. The horizontal axis is the slope (in ADC/cell) of a straight line fit to the average chip pedestal in bins of cell ID. This plot shows that there is a natural spread of pedestal slopes (vs. cell ID) that has a significant non-Gaussian positive tail. All chips measured for this plot have un-loaded inputs.