The following is a list of wafer probing tests performed at LBL with some rudimentary description: 1. AVDD and DVDD CURRENTS. After chip power-up we immediately check that there are no shorts inside the chip. In that case either AVDD or DVDD current can go up to the current limit of their corresponding supplies. We set both limits at 200 mA. If one or both currents hit this limit the die is classified as bad, and the test sequence for this die is aborted. The currents are also checked after some reasonable initialization and acquisition patterns have been run. The AVDD current depends on the preamp current settings. With the settings used for our tests, we reject chips if the AVDD current is below 55 mA or above 110 mA. Due to limitations of our setup, we can not measure the DVDD current while the chip is being read out (it is a tricky measurement because the readout time is short, and the current flows predominantly through the DVDD bypass capacitor). Instead, the DVDD current is measured when the chip just sits there, doing nothing. The chips are rejected if this current is below 4 mA or above 50 mA. 2. SERIAL LINE FUNCTIONALITY. Various sequences of 0s and 1s are sent to the chip shift register in the initialization mode. We check that whatever is sent on the top neighbor line shows up on the bottom neighbor line with the delay equal to the shift register depth. The dies which fail this test are immediately classified as bad and no further tests are performed on them. 3. BASIC READOUT FUNCTIONALITY and CHIP ID. A simple acquire-digitize-readout pattern is run with trigger in a known place. The readout stream is checked for errors in chip ids, cell ids, and channel numbers. Several chip ID settings are tried in order to make sure that there are no ID bits or readout bus bits which are stuck at 0 or 1. The dies which fail this test are also classified as bad immediately. 4. PEDESTALS and NOISE. Pedestals and noise are measured for all pipeline capacitors in the chip. This measurement is performed for two different preamp-pipeline polarity settings. The pedestal and the gain adjustment settings are fixed, as well as the pipeline depth. Pipeline capacitors and/or channels are marked as bad if pedestal, noise, or pedestal variations are out of limits. We want to accommodate die-to-die and wafer-to-wafer variations but to reject the chips which have too much noise and/or pedestal non-uniformity. The limit values are selected as a reasonable compromise between these two requirements, with the emphasis rather on allowing good dies to pass then on making bad dies to fail. As such, the noise limit is set to 5 ADC counts which for our clock and ramp resistor settings corresponds to about 5000 electrons. In the wafer testing setup we can not bypass the chips very well because the contacts are made through rather long probe card needles which have non-negligible inductance, and we have to average positive and negative polarity pedestals in order to cancel pedestal shifts produced by the trigger signal. This averaged pedestal has to be between 20 and 45 ADC counts (typical value for good chips is 30 counts with the RMS noise of about 1.3 counts). 5. CALIBRATION MASK. All calibration mask bits are set and calibration charge is injected into all channels simultaneously during the usual acquire-digitize-readout sequence. This is done for two different values of calibration voltage. In such way we can determine if the calibration works for every channel and can get a crude idea about the chip gain. The channels which do not appear to be sensitive to the calibration injection are marked as bad. 6. CHIP ADC LIMITS. During digitization, the ramp is kept at reset. As a result, the comparators which normally latch the ADC counter values never fire, and every channel should latch the value of "counter modulo" instead ("counter modulo"+-1 is also allowed). We go through various "counter modulo" settings and check that there are no bits stuck at 1 or 0 on any of the ADC latches. 7. PEDESTAL ADJUSTMENT. Ramp pedestal settings are stepped from 0 to 15 and the pedestals are measured for several channels with and without charge injection. This test is performed for two different polarity settings. For each die and for each pedestal settings, a median pedestal value is calculated over several selected channels. This value is compared to the median value over the whole wafer (known bad chips excluded). The difference between the chip median and the wafer median should be not more than 30 ADC counts and not less than -15 ADC counts for each pedestal setting. The assumption is, of course, that there are more than 50% of good chips in the sample remaining after removal of obviously bad dies. 8. DYNAMIC COMMON MODE SUPPRESSION. The number of channels with charge injection is changed (by changing calibration mask bits) within the range from about 30 to about 110, while chip is operating with common mode noise suppression turned on. We look at the average pedestal for several control channels. For these control channels the charge injection is always on. When the number of channels with charge injection becomes large, the common mode noise suppression circuit stops working (it is tricked into thinking that the charge injection IS the common mode noise), and it suppresses the control channels. We check when it happens and compare with what we expect for good dies. 9. GAIN. Chip gain is measured by changing calibration voltage in 50 mV steps so that it covers the whole dynamic range of the ADC. The gain is measured for all channels in a single pipeline cell and for all pipeline cells in a single channel. However, when the measurement is performed for all channels, charge is not injected into every channel (we think that the combined capacitance that has to be driven by the calibration voltage line is too large in this case). Instead, the charge is injected into every 10th channel and the measurement is performed 10 times with different calibration mask settings. We require that the gain is between 165 and 330 ADC counts per 1 Volt of the calibration injection voltage (typical good die gain is about 240 ADC counts / 1 V Vcal). 10. PIPELINE DELAY. Pipeline delay is checked for every setting from 1 to 42. The position of the trigger in the pattern is known, and the cell id which comes out is compared with the expected cell id. 11. SPARSIFICATION. Sparsification performance is checked in both "single channel" and "read neighbor" modes, with and without last chip flag. The sparsification threshold is set half-way between the pedestal level and the calibration signal level. The channels which come out are compared with the list of expected channels for several different calibration mask settings. 12. SPARSIFICATION THRESHOLD SCAN. Sparsification threshold is varied for about 20 counts above and below pedestal, and the number of channels which come out is recorded. The result should look like an S-curve. The location of the steepest part of that curve should coincide with the pedestal, and the width should be approximately equal to the chip noise. 13. BOTTOM NEIGHBOR. Transitions on the bottom neighbor line are monitored during digitization and readout in order to make sure that the neighbor logic and the priority passing work. 14. DATA VALID. We do not use data valid to write the chip data in our setup, so we check separately that it behaves as expected during readout. 15. GAIN ADJUSTMENT. The gain adjustment settings are varied from 0 to 255 with step of 10. As a result, the ramp rate and the observed pedestal should change accordingly. Note that we would probably like to start the SVX detector operation with some large value of gain adjustment and then gradually step down because the chip gain increases with accumulated dose. 16. MULTIHIT OPERATION. So far, all the above tests have been done in SVXII mode. In this test we inject 4 triggers first and then perform digitization and readout 4 times. The obtained cell ids are compared with the expected cell ids. We also require that the observed pedestal values from all triggers are between 18 and 55 ADC counts, and that the difference between different triggers is not more than 22 ADC counts. 17. DEADTIMELESS PERFORMANCE. An acquire-digitize-readout pattern is run, and another trigger is inserted into it in various places. This pattern is followed by a digitize-readout sequence for this second trigger. The obtained cell ids are compared with the expected cell ids. The original idea of this test was to look also at pedestals and noise. However, these data turned out to be unreliable during digitization or readout due to the lack of appropriate bypassing. Data integrity is checked in each test for every readout. This means that chip id, cell id, and channel numbers should come out right every time. For every test we perform not just a single acquisition, but a number of them. The number of acquisitions varies from 5 to 50, depending on the test length and complexity. The setup runs at 30 MHz, and the ramp reference resistor is 100K.