5 wafers were probed at random from each of the lots 10 and 11. All these wafers exhibited essentially 0 yield (you can find the wafer quality maps here, look for manufacturer serial numbers which have -10- and -11- in them). The problem was traced to a processing defect in vias which connect metal 2 to metal 3. The same defect is responsible for the "yield hole" in the central region of the wafers from lots 9 and 12. See Fermilab report TM-2081 by Ray Yarema for details. All wafers from lots 10 and 11 were returned to Honeywell.