200402LBL001

Thanks to Sven for these tests.

	Channel 0	Channel 1	Channel 2	Channel 3
Enable digital	Ok	Ok	Ok	OK
Enable analog	Ok	Ok	Ok	Ok
VDD@IDD~0.0A*	2.77 V (DAC=0) 1.27 V DAC=255)	2.74 V 1.27 V	2.72 V 1.26 V	2.75 V 1.27 V
VDD@IDD=1.0A*	2.38 V (DAC=0) 0.88 V (DAC=255)	2.35 V 0.88 V	2.33 V 0.87 V	2.36 V 0.87 V
IDD limit (when VDD goes to 0)	~ 1.25 A (DAC=0)	~ 1.22 A	~ 1.24 A	~ 1.26 A
IDD module ~= supplied current?	OK	OK	OK	OK
Set DAC dig works?	YES	YES	YES	OK
Read back  DAC dig works?	YES	YES	YES	YES
VDDA@IDDA=0.0A*	2.75V (DAC=0) 1.26V (DAC=255)	2.72 V 1.26 V	2.72 V 1.26 V	2.76 V 1.27 V
VDDA@IDDA=1.4A*	2.08 (DAC=0) 0.60 (DAC=255)	2.08 V 0.62 V	2.06 V 0.60 V	2.19 V 0.71 V
IDDA limit (when VDDA goes to 0)	~ 1.55 A (DAC=0)	1.52 A	1.52 A	1.51 A
IDDA module ~= supplied current?	YES	YES	YES	YES
Set DAC ana	YES	YES	YES	YES
Read back DAC ana	YES	yes	yes	yes
Thermal interlock	R7 = 15 k T = 37 C	R7 = 15 k T = 37	R7 = 15 k T = 37	R7 = 15 k T = 37 C
MCC test @ 160 MB/s (tests data lines) DTO2?	OK OK	OK OK	OK OK	Ok OK
Select Channel for Read	OK	OK	OK	OK
High Voltage routing	untested	OK	OK	OK
Perform a threshold scan with actual module (tests strobe + HV). Check noise.	untested	OK	OK	OK