1 ;-------------------------------------------------------- 2 ; File Created by SDCC : FreeWare ANSI-C Compiler 3 ; Version 2.4.0 Mon Mar 15 01:31:52 2004 4 5 ;-------------------------------------------------------- 6 .module dummy 7 .optsdcc -mmcs51 --model-small 8 9 ;-------------------------------------------------------- 10 ; Public variables in this module 11 ;-------------------------------------------------------- 12 .globl _main 13 .globl __vtable 14 .globl __firm_regulate 15 .globl __volt 16 .globl __adc 17 .globl __power_fail 18 .globl __resistor 19 .globl __buf 20 ;-------------------------------------------------------- 21 ; special function registers 22 ;-------------------------------------------------------- 23 ;-------------------------------------------------------- 24 ; special function bits 25 ;-------------------------------------------------------- 26 ;-------------------------------------------------------- 27 ; overlayable register banks 28 ;-------------------------------------------------------- 29 .area REG_BANK_0 (REL,OVR,DATA) 0000 30 .ds 8 31 ;-------------------------------------------------------- 32 ; internal ram data 33 ;-------------------------------------------------------- 34 .area DSEG (DATA) 35 ;-------------------------------------------------------- 36 ; overlayable items in internal ram 37 ;-------------------------------------------------------- 38 .area OSEG (OVR,DATA) 39 ;-------------------------------------------------------- 40 ; Stack segment in internal ram 41 ;-------------------------------------------------------- 42 .area SSEG (DATA) 0000 43 __start__stack: 0000 44 .ds 1 45 46 ;-------------------------------------------------------- 47 ; indirectly addressable internal ram data 48 ;-------------------------------------------------------- 49 .area ISEG (DATA) 50 ;-------------------------------------------------------- 51 ; bit data 52 ;-------------------------------------------------------- 53 .area BSEG (BIT) 54 ;-------------------------------------------------------- 55 ; external ram data 56 ;-------------------------------------------------------- 57 .area XSEG (XDATA) 0000 58 __buf:: 0000 59 .ds 30 001E 60 __resistor:: 001E 61 .ds 8 0026 62 __power_fail:: 0026 63 .ds 1 0027 64 __adc:: 0027 65 .ds 48 0057 66 __volt:: 0057 67 .ds 16 0067 68 __firm_regulate:: 0067 69 .ds 1 0068 70 __vtable:: 0068 71 .ds 1024 72 ;-------------------------------------------------------- 73 ; external initialized ram data 74 ;-------------------------------------------------------- 75 .area XISEG (XDATA) 76 ;-------------------------------------------------------- 77 ; interrupt vector 78 ;-------------------------------------------------------- 79 .area CSEG (CODE) 0000 80 __interrupt_vect: 0000 02s00r00 81 ljmp __sdcc_gsinit_startup 0003 32 82 reti 0004 83 .ds 7 000B 32 84 reti 000C 85 .ds 7 0013 32 86 reti 0014 87 .ds 7 001B 32 88 reti 001C 89 .ds 7 0023 32 90 reti 0024 91 .ds 7 002B 32 92 reti 93 ;-------------------------------------------------------- 94 ; global & static initialisations 95 ;-------------------------------------------------------- 96 .area GSINIT (CODE) 97 .area GSFINAL (CODE) 98 .area GSINIT (CODE) 0000 99 __sdcc_gsinit_startup: 0000 75 81rFF 100 mov sp,#__start__stack - 1 0003 12s00r00 101 lcall __sdcc_external_startup 0006 E5 82 102 mov a,dpl 0008 60 03 103 jz __sdcc_init_data 000A 02s00r2C 104 ljmp __sdcc_program_startup 000D 105 __sdcc_init_data: 106 ; _mcs51_genXINIT() start 000D 79r00 107 mov r1,#l_XINIT 000F E9 108 mov a,r1 0010 44s00 109 orl a,#(l_XINIT >> 8) 0012 60 1B 110 jz 00003$ 0014 7As00 111 mov r2,#((l_XINIT+255) >> 8) 0016 90s00r00 112 mov dptr,#s_XINIT 0019 78r00 113 mov r0,#s_XISEG 001B 75 A0s00 114 mov p2,#(s_XISEG >> 8) 001E E4 115 00001$: clr a 001F 93 116 movc a,@a+dptr 0020 F2 117 movx @r0,a 0021 A3 118 inc dptr 0022 08 119 inc r0 0023 B8 00 02 120 cjne r0,#0,00002$ 0026 05 A0 121 inc p2 0028 D9 F4 122 00002$: djnz r1,00001$ 002A DA F2 123 djnz r2,00001$ 002C 75 A0 FF 124 mov p2,#0xFF 002F 125 00003$: 126 ; _mcs51_genXINIT() end 127 ; _mcs51_genRAMCLEAR() start 002F 78r00 128 mov r0,#l_XSEG 0031 E8 129 mov a,r0 0032 44s00 130 orl a,#(l_XSEG >> 8) 0034 60 0C 131 jz 00005$ 0036 79s00 132 mov r1,#((l_XSEG + 255) >> 8) 0038 90s00r00 133 mov dptr,#s_XSEG 003B E4 134 clr a 003C F0 135 00004$: movx @dptr,a 003D A3 136 inc dptr 003E D8 FC 137 djnz r0,00004$ 0040 D9 FA 138 djnz r1,00004$ 0042 F6 139 00005$: mov @r0,a 0043 D8 FD 140 djnz r0,00005$ 141 ; _mcs51_genRAMCLEAR() end 142 .area GSFINAL (CODE) 0000 02s00r2C 143 ljmp __sdcc_program_startup 144 ;-------------------------------------------------------- 145 ; Home 146 ;-------------------------------------------------------- 147 .area HOME (CODE) 148 .area CSEG (CODE) 149 ;-------------------------------------------------------- 150 ; code 151 ;-------------------------------------------------------- 152 .area CSEG (CODE) 002C 153 __sdcc_program_startup: 002C 12s00r31 154 lcall _main 155 ; return from main will lock up 002F 80 FE 156 sjmp . 157 ;------------------------------------------------------------ 158 ;Allocation info for local variables in function 'main' 159 ;------------------------------------------------------------ 160 ;------------------------------------------------------------ 161 ;dummy.c:4: void main () 162 ; ----------------------------------------- 163 ; function main 164 ; ----------------------------------------- 0031 165 _main: 0002 166 ar2 = 0x02 0003 167 ar3 = 0x03 0004 168 ar4 = 0x04 0005 169 ar5 = 0x05 0006 170 ar6 = 0x06 0007 171 ar7 = 0x07 0000 172 ar0 = 0x00 0001 173 ar1 = 0x01 174 ;dummy.c:6: while (1); 0031 175 00102$: 176 ; Peephole 112.b changed ljmp to sjmp 0031 80 FE 177 sjmp 00102$ 0033 178 00104$: 0033 22 179 ret 180 .area CSEG (CODE) 181 .area XINIT (CODE)