SVX3D Wafer Quality Maps
4-in Wafer Maps
- First Honeywell batch of SVX3D chips
- Second Honeywell batch of SVX3D chips
- Combined quality map for 118 wafers from 4-in batches
6-in Wafer Maps
- 6-in SVX3D wafers from lot 8
- Combined quality map for wafers from lot 8
- 6-in wafers from lots 9 and 12
- Combined quality map for wafers from lots 9 and 12
- Maps for lots 13 and 14
- Maps for lot 15
- Maps for lot 16
Yield Summaries
- Test procedures and yield summary for the 4-in Honeywell run
- Yields for the 4-in run and 6-in lots 8, 9, 12
- The story about lots 10 and 11
- Yield summary for 6-in lots 13, 14, and 15
Special Yield Studies
- 4-in wafers probed before backgrinding and backplating
- 6-in wafers probed before backgrinding and backplating
- Maps for annealed wafers
Talks
- SVXII chip count
- Testing Front-End Electronics for the CDF Silicon Upgrade